1. Field of the Invention
The present invention relates to circuit board structures and fabrication methods thereof, and more particularly, to a circuit board structure without a core and a fabrication method thereof.
2. Description of Related Art
As electronic industry is ever-developing, a multilayer circuit board having a plurality of active elements, passive elements and circuits is provided to meet requirements of packaging for high integration and microminiaturization of a semiconductor package. More usable layout space of the multilayer circuit board in a limited area is obtained by interlayer connection technology so as to satisfy the requirements of high density of integrated circuit. A build-up method is disclosed in prior art to improve precision of the layout of a multilayer circuit board. The method comprises the steps of: Providing a core board having a plurality of inner circuit layers on the upper side and the lower side of the core board and conductive holes through the core board to connect electrically the inner circuit layers; stacking a plurality of dielectric layers and circuit layers alternately on upper and lower surfaces of the core board and forming conductive vias in the dielectric layers to establish electrical connection between the circuit layers.
Referring to FIG. 1A to FIG. 1H, there are shown schematic views of a process of fabricating a multiplayer circuit board according to the prior art.
As shown in FIG. 1A, a copper-coated laminated (CCL) core 100 with metallic thin layers 101 is provided, and a plurality of holes 102 are formed in the core 100 by drilling.
As shown in FIG. 1B, metallic layers 103 are formed on the surface of the metallic thin layers 101 and walls of the holes 102.
As shown in FIG. 1C, plated-through holes (PTH) 102a are formed by filling the holes 102 with conducting or non-conducting stuffing materials 11, such as insulating ink, copper-containing conductive paste or the like, so as to enable electrical conduction between the upper and lower metallic layers 103 on the core 100.
As shown in FIG. 1D, the surfaces of the metallic layers 103 flatten out after a surplus portion of the stuffing material 11 has been removed by a scrubbing process.
As shown in FIG. 1E, a circuit patterning process is performed on the metallic thin layers 101 and the metallic layers 103 on the core 100, so as to finalize a substrate 10 with inner circuit layers 104 formed on two opposing sides of the substrate 10, respectively.
As shown in FIG. 1F, dielectric layers 12 are formed on the inner circuit layers 104 formed on upper and lower surfaces of the substrate 10, and a plurality of vias 120 are formed in the dielectric layers 12 by laser drilling.
As shown in FIG. 1G, conductive layers 13 are formed on the surface of the dielectric layers 12 and the vias 120. Resist layers 14 are formed on the conductive layers 13. Opening regions 140 which expose a portion of the conductive layers 13 to the outside are formed in the resist layers 14 to allow an electroplating process to be performed. Circuit layers 15 are formed on the conductive layers 13 exposed from the opening regions 140 by the electroplating process, and conductive vias 151 are formed in the vias 120 such that the circuit layers 15 are electrically connected to the inner circuit layers 104.
As shown in FIG. 1H, a multilayer circuit board is formed by removing the conductive layers 13 and the resist layers 14 thereon and repeating the steps of the formation of the dielectric layers and circuit layers of the FIG. 1F and FIG. 1G.
However, the manufacturing process of said multiplayer circuit board comprises the steps of providing the core 100 with the metallic thin layers 101 thereon, forming the plurality of plated-through holes 102a in the core 100, and forming the inner circuit layers 104 on the surface of the core 100 to thereby require operations, such as drilling, plugging, and scrubbing, which render the manufacturing process complicated.
In addition, the diameter of the plated-through holes 102a formed by circuit-electroplating in the substrate 10 is about 100 μm above and the diameter of the conductive vias 151 formed by circuit-electroplating in the dielectric layers 12 is around 50 μm. Therefore the structure of the plating-through holes 102a occupies more layout space than the conductive vias 151 to the detriment of formation of a fine-pitch circuit structure.
Moreover, the dielectric layers 12 are composed of prepreg. The dielectric layers 12 are formed on the fine-pitch inner circuit layers 104 of the substrate 10. However, it is difficult to stuff the prepreg into the space between the circuits in the inner circuit layers 104. Hence, the dielectric layers 12 are not each sufficiently bonded to the substrate 10 and thus gaps are created therebetween, and in consequence the dielectric layers 12 are detachable from the substrate 10 during a follow-up process.
Furthermore, the multilayer circuit board is unnecessarily thick to the detriment of miniaturization, because the core 100 occupies most of the substrate 10.
Therefore, it is imperative to provide a multilayer circuit board and a fabrication method thereof so as to overcome the above-described drawbacks, such as small layout density, the need for formation of the dielectric layers, and excessive thickness of the circuit board.